There is a current interest in CMOS active pixel imagers for possible use as low cost imaging devices. An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to FIG. 1. Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies and promise higher readout rates compared to passive pixel sensors. The FIG. 1 exemplary pixel cell 10 is a 4T APS, where the 4T is commonly used in the art to designate use of four transistors to operate the pixel. A 4T pixel has a photodiode 162, a reset transistor 184, a transfer transistor 182, a source follower transistor 186, and a row select transistor 188. It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, and that in practical use there will be an M times N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The pixel cell 150 includes the photodiode 162 which converts incident photons to electrons. The electrons are passed to a collection node A by transfer transistor 182. A source follower transistor 186 has its gate connected to node A and thus amplifies the signal appearing at Node A. When a particular row containing cell 150 is selected by a row selection transistor 188, the signal amplified by transistor 186 is passed on a column line 170 to the readout circuitry. The photodiode 162 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager may include a photogate or other photon to charge converting device, in lieu of a photodiode, as the initial accumulator for photo-generated charge.
The gate of transfer transistor 182 is coupled to a transfer control signal (tx) line 180, thereby serving to control the coupling of the photodiode 162 to the node A. A reset voltage source Vrst is coupled by conductive line 163 through reset transistor 184 to node A. The gate of reset transistor 184 is coupled to a reset control line rst 190 which serves to control the reset operation in which Vrst is connected to node A. The row select control line 160 is coupled to all of the pixels of the same row of the array. Voltage source Vdd is coupled to column line 170 by conductive line 165 through transistors 186 and 188. Although not shown in FIG. 1, column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink at its lower end. The gate of row select transistor 188 is coupled to row select control line 160. The Vrst power supply is typically connected to the Vdd power supply, so that the Vrst voltage is equivalent to Vdd (e.g., Vdd_pix).
As known in the art, a value is read from pixel 150 in a two step process. First, node A is reset by turning on reset transistor 184 and the reset voltage (e.g., Vrst) is read out to column line 170 by the source follower transistor 186 through the activated row select transistor 188. Second, after pixel reset, a charge integration period occurs during which the photodiode 162 converts photons to electrons. After the integration period, transfer transistor 182 turns on and the integrated charge is passed by transfer transistor from the photodiode 162 to node A, where it is amplified by source follower transistor 186 and passed to column line 170 by row access transistor 188. As a result, the two different values—the reset voltage and the signal voltage—are readout from the pixel and sent by the column line 170 to the readout circuitry where each is sampled and held for further processing as known in the art.
All pixels in a row are read out simultaneously onto respective column lines 170 and the column lines are activated in sequence for pixel reset and signal voltage read out. The rows of pixels are read out in sequence onto the respective column lines.
FIG. 2 shows an exemplary CMOS active pixel sensor integrated circuit chip that includes an array of active pixel sensors 230 and a controller 232 which provides timing and control signals to enable reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M times N pixels, with the size of the array 230 depending on a particular application. The imager is read out a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Charge signals stored in the selected row of pixels are provided on the column lines 170 to a readout circuit 242 in the manner described above. The pixel signal read from each of the columns then can be read out sequentially using a column addressing circuit 244. Differential pixel signals (Vrst, Vsig) corresponding to the read out reset signal and integrated charge signal are provided as respective outputs Vout1, Vout2 of the readout circuit 242.
FIG. 3 more closely shows the rows and columns 349 of CMOS active pixel sensors 350. Each column includes multiple rows of sensors 350. Signals from the active pixel sensors 350 in a particular column can be read out to a readout circuit 352 associated with that column. The read out circuit 352 includes sample and hold circuitry for acquiring the pixel reset and integrated charge signals. Signals stored in the readout circuits 352 then can be read sequentially column-by-column to an output stage 354 which is common to the entire array of pixels 330. The analog output signals can then be sent, for example, to a differential analog circuit and which subtracts the reset and integrated charge signals and sends them to an analog-to-digital converter (ADC) or the reset and integrated charge signals are each supplied to the analog-to-digital converter.
As fabrication techniques get better an increasing number of digital processing circuits are being implemented on the same chip as an image sensor. This increases substrate noise coupling to a pixel, which can compromise the signal to noise ratio of the image sensor core. The substrate noise occurs when spurious noise signals are injected locally into the substrate through ohmic or capacitive coupling, thereby breaking the equipotentiality of the substrate.
Accordingly, when the reset signal and the integrated charge signal are read out at different times, the potential of the local ground may not be the same. The sensing node A (FIG. 1) of each pixel is capacitively coupled to a local ground and is dynamically affected by local substrate noise. The common mode noise, including ground noise, during the reset phase is Vcm1 and during the signal phase is Vcm2. If Vsig is the signal voltage and Vrst is the reset voltage, then the differential voltage Vdiff=(Vsig+Vcm2)−(Vrst+Vcm1). Since Vcm2 does not equal Vcm1, they do not cancel out in the differential signal, and instead adversely affect the pixel signal ultimately produced.
One way of dealing with substrate noise is to use a dummy circuit, similar to a pixel circuit, and located near the pixel circuit, but shielded from light as a reference signal source. Theoretically, the pixel and dummy circuit would see the same substrate voltage which can then be correlated in processing. But this will cause a decreased fill factor for the pixels, and for some architectures will cause an increase in KTC (thermal) noise.
It would be desirable to have a pixel readout circuit that compensates for substrate and other common mode noise that is encountered during a pixel read out operation.